This application contains subject matter related to the subject matter disclosed in U.S. patent application Ser. Nos. 09/776,750 and 09/776,747, both filed on Feb. 6, 2001.
1. Field of the Invention
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to copper and copper alloy metallization in semiconductor devices.
2. Background of the Invention
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing sub-micron-sized, low resistance-capacitance (RC) metallization patterns. This is particularly applicable when the sub-micron-features, such as vias, contact areas, lines, trenches, and other shaped openings or recesses have high aspect ratios (depth-to-width) due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, usually of doped monocrystalline silicon (Si), and a plurality of sequentially formed inter-metal dielectric layers and electrically conductive patterns. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns of vertically spaced metallization levels are electrically interconnected by vertically oriented conductive plugs filling via holes formed in the inter-metal dielectric layer separating the metallization levels, while other conductive plugs filling contact holes establish electrical contact with active device regions, such as a source/drain region of a transistor, formed in or on a semiconductor substrate. Conductive lines formed in trench-like openings typically extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type according to current technology may comprise five or more levels of metallization to satisfy device geometry and microminiaturization requirements.
A commonly employed method for forming conductive plugs for electrically interconnecting vertically spaced metallization levels is known as xe2x80x9cdamascenexe2x80x9d-type processing. Generally, this process involves forming a via opening in the inter-metal dielectric layer or interlayer dielectric (ILD) between vertically spaced metallization levels which is subsequently filled with metal to form a via electrically connecting the vertically spaced apart metal features. The via opening is typically formed using conventional lithographic and etching techniques. After the via opening is formed, the via is filled with a conductive material, such as tungsten (W), using conventional techniques, and the excess conductive material on the surface of the inter-metal dielectric layer is then typically removed by chemical mechanical planarization (CMP).
A variant of the above-described process, termed xe2x80x9cdual damascenexe2x80x9d processing, involves the formation of an opening having a lower contact or via opening section which communicates with an upper trench section. The opening is then filled with a conductive material to simultaneously form a contact or via in contact with a conductive line. Excess conductive material on the surface of the inter-metal dielectric layer is then removed by CMP. An advantage of the dual damascene process is that contact or via and the upper line are formed simultaneously.
High performance microprocessor applications require rapid speed of semiconductor circuitry, and the integrated circuit speed varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As integration density increases and feature size decreases, in accordance with submicron design rules, the rejection rate due to integrated circuit speed delays significantly reduces manufacturing throughput and increases manufacturing costs.
One way to increase the circuit speed is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notably aluminum (Al) or an alloy thereof, and etching, or by damascene techniques. Al is conventionally employed because it is relatively inexpensive, exhibits low resistivity and is relatively easy to etch. However, as the size of openings for vias/contacts and trenches is scaled down to the submicron range, step coverage problems result from the use of Al. Poor step coverage causes high current density and enhanced electromigration. Moreover, low dielectric constant polyamide materials, when employed as inter-metal dielectric layers, create moisture/bias reliability problems when in contact with Al, and these problems have decreased the reliability of interconnections formed between various metallization levels.
One approach to improved interconnection paths in vias involves the use of completely filled plugs of a metal, such as W. Accordingly, many current semiconductor devices utilizing VLSI (very large scale integration) technology employ Al for the metallization level and W plugs for interconnections between the different metallization levels. The use of W, however, is attendant with several disadvantages. For example, most W processes are complex and expensive. Furthermore, W has a high resistivity, which decreases circuit speed. Moreover, Joule heating may enhance electromigration of adjacent Al wiring. Still a further problem is that W plugs are susceptible to void formation, and the interface with the metallization level usually results in high contact resistance.
Another attempted solution for the Al plug interconnect problem involves depositing Al using chemical vapor deposition (CVD) or physical vapor deposition (PVD) at elevated temperatures. The use of CVD for depositing Al is expensive, and hot PVD Al deposition requires very high process temperatures incompatible with manufacturing integrated circuitry.
Copper (Cu) and Cu-based alloys are particularly attractive for use in VLSI and ULSI semiconductor devices, which require multi-level metallization levels. Cu and Cu-based alloy metallization systems have very low resistivities, which are significantly lower than W and even lower than those of previously preferred systems utilizing Al and its alloys. Additionally, Cu has a higher resistance to electromigration. Furthermore, Cu and its alloys enjoy a considerable cost advantage over a number of other conductive materials, notably silver (Ag) and gold (Au). Also, in contrast to Al and refractory-type metals (e.g., titanium (Ti), tantalum (Ta) and W), Cu and its alloys can be readily deposited at low temperatures formed by well-known xe2x80x9cwetxe2x80x9d plating techniques, such as electroless and electroplating techniques, at deposition rates fully compatible with the requirements of manufacturing throughput.
Electroless plating of Cu generally involves the controlled auto-catalytic deposition of a continuous film of Cu or an alloy thereof on a catalytic surface by the interaction of at least a Cu-containing salt and a chemical reducing agent contained in a suitable solution, whereas electroplating comprises employing electrons supplied to an electrode (comprising the surface(s) to be plated) from an external source (i.e., a power supply) for reducing Cu ions in solution and depositing reduced Cu metal atoms on the plating surface(s). In either case, a nucleation/seed layer is required for catalysis and/or deposition on the types of substrates contemplated herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
Another technique to increase the circuit speed is to reduce the capacitance of the inter-metal dielectric layers. Dielectric materials such as silicon oxide (SiO2) have been commonly used to electrically separate and isolate or insulate conductive elements of the integrated circuit from one another. However, as the spacing between these conductive elements in the integrated circuit structure has become smaller, the capacitance between such conductive elements because of the dielectric being formed from silicon oxide is more of a concern. This capacitance negatively affects the overall performance of the integrated circuit because of increased power consumption, reduced speed of the circuitry, and cross-coupling between adjacent conductive elements.
A response to the problem of capacitance between adjacent conductive elements caused by use of silicon oxide dielectrics has led to the use of other dielectric materials, commonly known as low-k dielectrics. Whereas silicon oxide has a dielectric constant of approximately 4.0, many low-k dielectrics have dielectric constants less than 3.5. Examples of low-k dielectric materials include organic or polymeric materials. Another example is porous, low density materials in which a significant fraction of the bulk volume contains air, which has a dielectric constant of approximately 1. The properties of these porous materials are proportional to their porosity. For example, at a porosity of about 80%, the dielectric constant of a porous silica film, i.e. porous SiO2, is approximately 1.5. Still another example of a low-k dielectric material is carbon doped silicon oxide wherein at least a portion of the oxygen atoms bonded to the silicon atoms are replaced by one or more organic groups such as, for example, an alkyl group such as a methyl (CH3xe2x80x94) group.
A problem associated with the use of many low-k dielectric materials is that these materials can be damaged by exposure to oxidizing or xe2x80x9cashingxe2x80x9d systems, which remove a resist mask used to form openings, such as vias, in the low-k dielectric material. This damage can cause the surface of the low-k dielectric material to become a water absorption site, if and when the damaged surface is exposed to moisture. Subsequent processing, such as annealing, can result in water vapor formation, which can interfere with subsequent filling with a conductive material of a via/opening or a damascene trench formed in the dielectric layer. For this reason, the upper surface of the low-k dielectric material is typically protected from damage during removal of the resist mask by a capping layer, such as silicon oxide, disposed over the upper surface.
A number of different variations of a damascene process using low-k dielectrics have been employed during semiconductor manufacturing. With reference to FIGS. 1A-1H, an example of a damascene process for forming vias between vertically spaced metallization levels, according to conventional techniques, will be described. This process can be repeated to form multiple metallization levels, i.e., two or more, stacked one on top of another.
In FIG. 1A, a first etch stop layer 12 is deposited over a first metallization level 10. The first etch stop layer 12 acts as a passivation layer that protects the first metallization level 10 from oxidation and contamination and prevents the material of the metallization level 10 from diffusing into a subsequently formed dielectric layer. The first etch stop layer 12 also acts as an etch stop during subsequent etching of the dielectric layer. A typical material used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the metallization level 10 to form the first etch stop layer 12. An illustrative process used for depositing silicon nitride is plasma enhanced CVD (PECVD).
In FIG. 1B, a first low-k dielectric layer 14 is deposited over the first etch stop layer 12. The majority of low-k dielectric materials used for a dielectric layer are based on organic or inorganic polymers. The liquid dielectric material is typically spun onto the surface under ambient conditions to a desired depth. This is typically followed by a heat treatment to evaporate solvents present within the liquid dielectric material and to cure the film to form the first low-k dielectric layer 14.
After formation of the first low-k dielectric layer 14, a capping layer 13 can be formed over the first low-k dielectric layer 14. The function of the capping layer 13 is to protect the first low-k dielectric layer 14 from the process that removes a subsequently formed resist layer. The capping layer 13 can also be used as a mechanical polishing stop to prevent damage to the first low-k dielectric layer 14 during subsequent polishing away of conductive material that is deposited over the first low-k dielectric layer 14 and in a subsequently formed via. Examples of materials used as a capping layer 13 include silicon oxide and silicon nitride.
In FIG. 1C, vias 16 are formed in the first low-k dielectric layer 14 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 17 over the capping layer 13 and exposing and developing the resist 17 to form the desired patterns of the vias 16. The first etch, which is highly selective to the material of the first low-k dielectric layer 14 and the capping layer 13, removes the capping layer 13 and the first low-k dielectric layer 14 until the etchant reaches the first etch stop layer 12. The first etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the first low-k dielectric layer 14 directly below the opening in the resist 17. By using an anisotropic etch, the via 16 can be formed with substantially perpendicular sidewalls.
In FIG. 1D, a second etch, which is highly selective to the material of the first etch stop layer 12, removes the first etch stop layer 12 until the etchant reaches the first metallization level 10. The second etch is also typically an anisotropic etch.
In FIG. 1E, the corners 18 of the vias 16 can be rounded using a reverse physical sputtering process. The corners 18 of the vias 16 are rounded to prevent problems of void creation associated with subsequent deposition of the conductive plug, and if necessary, a barrier layer. The reverse sputtering process can also be used to clean the first metallization level 10 at the bottom of the via 16. Incomplete etching of the first etch stop layer 12 can leave a portion of the first etch stop layer 12 over the first metallization level 10, and this material can prevent good ohmic contact between the material of the conductive plug and the material of the first metallization level 10. Use of the reverse sputtering process, however, can remove any remaining material of the first etch stop layer 12 and any other contaminants on the first metallization level 10.
In FIG. 1F, an adhesion/barrier material, such as tantalum, titanium, tungsten, tantalum nitride, or titanium nitride, is deposited. The combination of the adhesion and barrier material is collectively referred to as a second diffusion barrier layer 20. The second diffusion barrier layer 20 acts to prevent diffusion into the first low-k dielectric layer 14 of the conductive material subsequently deposited into the via 16.
In FIG. 1G, a layer 22 of a conductive material, for example, a Cu or Cu-based alloy, is deposited into the via 16 and over the dielectric layer 14. A typical process initially involves depositing a xe2x80x9cseedxe2x80x9d layer on the second diffusion barrier layer 20 subsequently followed by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the via 16. So as to ensure complete filling of the via 16, the Cu-containing conductive layer 22 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer 24 so as to overfill the via 16 and cover the upper surface 26 of the capping layer 13.
In FIG. 1H, the entire excess thickness of the metal overburden layer 24 over the upper surface 26 of the capping layer 13 is removed using a CMP process. A typical CMP process utilizes an alumina (Al2O3)-based slurry and leaves a conductive plug in the via 16. The conductive plug has an exposed upper surface 30, which is substantially co-planar with the surface 26 of the capping layer 13.
A number of different variations of a dual damascene process using low-k dielectrics have been employed during semiconductor manufacturing. With reference to FIGS. 2A-2L, a dual damascene process for forming vias and a second metallization level over a first metallization level, according to conventional techniques, will be described. This process can be repeated to form multiple metallization levels, i.e., two or more, stacked one on top of another.
In FIG. 2A, a second etch stop layer 12 is deposited over a first metallization level 10. The second etch stop layer 12 acts as a passivation layer that protects the first metallization level 10 from oxidation and contamination and prevents diffusion of material from the metallization level 10 into a subsequently formed dielectric layer. The second etch stop layer 12 also acts as an etch stop during subsequent etching of the dielectric layer. A typical material used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the metallization level 10 to form the second etch stop layer 12. An illustrative process used for depositing silicon nitride is PECVD.
In FIG. 2B, a first low-k dielectric layer 14 is deposited over the second etch stop layer 12. The majority of low-k dielectric materials used for a dielectric layer are based on organic or inorganic polymers. The liquid dielectric material is typically spun onto the surface under ambient conditions to a desired depth. This is typically followed by a heat treatment to evaporate solvents present within the liquid dielectric material and to cure the film to form the first low-k dielectric layer 14.
In FIG. 2C, a first etch stop layer 40 is deposited over the first low-k dielectric layer 14. The first etch stop layer 40 acts as an etch stop during etching of a dielectric layer subsequently formed over the first etch stop layer 40. As with the second etch stop layer 12, a material typically used as an etch stop is silicon nitride, and approximately 500 angstroms of silicon nitride is typically deposited over the first dielectric layer 40 to form the first etch stop layer 40. An illustrative process used for depositing silicon nitride is PECVD.
In FIG. 2D, a second low-k dielectric layer 42 is deposited over the first etch stop layer 40. After formation of the second low-k dielectric layer 42, a capping layer 13 can be formed over the second low-k dielectric layer 42. The function of the capping layer 13 is to protect the second low-k dielectric layer 42 from the process that removes a subsequently formed resist layer. The capping layer 13 can also be used as a mechanical polishing stop to prevent damage to the second low-k dielectric layer 42 during subsequent polishing away of conductive material that is deposited over the second low-k dielectric layer 42 and in a subsequently formed via and trench. Examples of materials used as a capping layer 13 include silicon oxide and silicon nitride.
In FIG. 2E, the pattern of the vias are formed in the second low-k dielectric layer 42 and capping layer 13 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 44 over the capping layer 13 and exposing and developing the resist 44 to form the desired pattern of the vias. The first etch, which is highly selective to the material of the second low-k dielectric layer 42 and capping layer 13, removes the capping layer 13 and the second low-k dielectric layer 42 until the etchant reaches the first etch stop layer 40. The first etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the second low-k dielectric layer 42 directly below the opening in the resist 44.
In FIG. 2F, a second etch, which is highly selective to the material of the first etch stop layer 40, removes the first etch stop layer 40 until the etchant reaches the first low-k dielectric layer 14. The second etch is also typically an anisotropic etch.
In FIG. 2G, the vias 16 are formed in the first low-k dielectric layer 14 and the trenches 46 of the second metallization level are formed in the second low-k dielectric layer 42 using conventional lithographic and etch techniques. The lithographic process involves depositing a resist 50 over the capping layer 13 and exposing and developing the resist 50 to form the desired pattern of the trenches 46. The third etch, which is highly selective to the material of the first and second dielectric layers 14, 42, removes the first low-k dielectric layer 14 until the etchant reaches the second etch stop layer 12 and removes the second low-k dielectric layer 42 until the etchant reaches the first etch stop layer 40. The third etch is typically an anisotropic etch, such as a reactive ion plasma dry etch, that removes only the exposed portions of the first low-k dielectric layer 14 directly below the opening in the first etch stop layer 40 and the exposed portions of the second low-k dielectric layer 42 directly below the opening in the resist 50. By using an anisotropic etch, the via 16 and the trench 46 can be formed with substantially perpendicular sidewalls.
In FIG. 2H, a fourth etch, which is highly selective to the material of the first and second etch stop layers 40, 12, then removes the second etch stop layer 12 until the etchant reaches the first metallization level 10 and removes the first etch stop layer 40 until the etchant reaches the first low-k dielectric layer 14. The fourth etch is also typically an anisotropic etch.
In FIG. 2I, the corners 18 of the vias 16 and trenches 46 can be rounded using a reverse sputtering process. The corners 18 of the vias 16 and trenches 46 are rounded to prevent problems of void creation associated with subsequent deposition of the conductive plug and second metallization level, and if necessary, a barrier layer. The reverse sputtering process can also be used to clean the first metallization level 10 at the bottom of the via 16. Incomplete etching of the second etch stop layer 12 can leave a portion of the second etch stop layer 12 over the first metallization level 10, and this material can prevent good ohmic contact between the material of the conductive plug and the material of the first metallization level 10. Use of the reverse sputtering process, however, can remove any remaining material of the second etch stop layer 12 and any other contaminants on the first metallization level 10.
In FIG. 2J, an adhesion/barrier material, such as tantalum, titanium, tungsten, tantalum nitride, or titanium nitride, is deposited. The combination of the adhesion and barrier material is collectively referred to as a second diffusion barrier layer 20. The second diffusion barrier layer 20 acts to prevent diffusion into the first and second dielectric layers 14, 42 of the conductive material subsequently deposited into the via 16 and trench 46.
In FIG. 2K, a layer 22 of a conductive material, for example, a Cu or Cu-based alloy, is deposited in the via 16 and trench 46 and over the capping layer 13. A typical process initially involves depositing a xe2x80x9cseedxe2x80x9d layer on the barrier layer 20 subsequently followed by conventional plating techniques, e.g., electroless or electroplating techniques, to fill the via 16 and trench 46. So as to ensure complete filling of the via 16 and trench 46, the Cu-containing conductive layer 22 is deposited as a blanket (or xe2x80x9coverburdenxe2x80x9d) layer 24 so as to overfill the trench 46 and cover the upper surface 52 of the capping layer 13.
In FIG. 2L, the entire excess thickness of the metal overburden layer 24 over the upper surface 52 of the capping layer 13 is removed using a CMP process. A typical CMP process utilizes an alumina (Al2O3)-based slurry, which leaves a conductive plug in the via 16 and a second metallization level in the trench 46. The second metallization level has an exposed upper surface 58, which is substantially co-planar with the upper surface 52 of the capping layer 13.
A problem that can be caused by the use of Cu and Cu-based alloys results from Cu having a relatively large diffusion coefficient into silicon oxide and silicon. Once Cu has diffused into these materials, Cu can cause the dielectric strength of these materials to decrease and cause a lack of uniformity in the overall properties of the semiconductor device produced. This problem is particularly prevalent if the dielectric layer has a high porosity as copper can more easily leach, or migrate, into the pores of,the dielectric layer. If Cu from the plug or the metallization level diffuses into the dielectric layer, the layer can become more conductive, and this increase in conductivity can cause short circuits between adjacent conductive regions. These short circuits can therefore result in failure of the semiconductor device. For this reason, Cu conductors are encapsulated by at least one diffusion barrier to prevent diffusion of the Cu into the silicon oxide layer.
The above-described processes, however, can still result in copper contamination as a result of the use of reverse physical sputtering or sputter etching to clean the first metallization level and to round the corners of the trenches and vias. Reverse physical sputtering or sputter etching is a process by which atoms or molecules from the surface of a material are dislocated or removed by the impact energy of gas ions, which are accelerated in an electric field. This process involves the creation of a glow discharge or plasma between an anode and a cathode, such as a semiconductor device, wherein the current therebetween is composed of electron flow to the anode and positive ion flow to the cathode. The ions are created by the ionization of gas molecules, such as argon, existing within the flow discharge region between the anode and cathode. The ionization results from the collision of gas particles with the electron flow from the cathode to the anode. A focused beam of these ions can be directed to a very small point on a semiconductor device and then scanned, raster fashion, over a surface where material is to be removed. As an ion impinges on the semiconductor device surface, momentum is transferred from the ion to the impact surface resulting in the removal of one or more surface atoms.
The problem of copper contamination as a result of reverse sputtering is illustrated in FIG. 3. The reverse physical sputtering process rounds the corners 18 of the vias 16 and trenches 46 as a result of ionized argon impacting the corners 18 and dislodging atoms. As the atoms of argon are impacting the corners 18, the atoms of argon are also impacting all the other exposed surfaces, such as the Cu of the first metallization level 10. Thus, the impact of the argon atoms onto the first metallization level 10 also dislodges atoms of Cu, and the dislodged atoms of Cu are free to be redeposited on other surfaces. In particular, the dislodged Cu atoms can be deposited onto the exposed sidewall surfaces 15 of the first and second low-k dielectric layers 14, 42. Once the Cu is deposited on the first and second low-k dielectric layers 14, 42, the Cu can then diffuse into the first and second low-k dielectric layers 14, 42. As previously stated, the diffusion of Cu into a low-k dielectric layer 14, 42 causes detrimental effects that can result in the failure of the semiconductor device. The problem of Cu diffusion into the dielectric layers 14, 42 is particularly pronounced when the low-k dielectric material is porous.
Another problem associated with above-identified processes is the limited choices of material for the etch stop layers. A commonly used material as an etch stop is silicon nitride, which has a dielectric constant of about 7.0. However, the use of a thick etch stop layer of silicon nitride with a low-k dielectric layer partially negates the benefits obtained by use of a low-k dielectric material because of the increased combined capacitance of the etch stop layer and dielectric layer. Accordingly, a need exists for an improved method of forming copper plugs and copper metallization with low-k dielectric layers that allows for use of reverse sputtering to round corners of vias, so as to minimize the problem of void creation, yet still prevent the low-k dielectric layers from being contaminated with Cu.
This and other needs are met by embodiments of the present invention which provide a semiconductor device, which includes a first metallization level, a first diffusion barrier layer, a second etch stop layer, a first etch stop layer, a dielectric layer, and an opening. The first diffusion barrier layer is formed from a first material disposed over the first metallization level. The second etch stop layer is formed from a second material disposed over the first diffusion barrier layer, and the first material is different from the second material. The first etch stop layer is disposed on the second etch stop layer with a first interface therebetween, and the dielectric layer is disposed over the first etch stop layer. The opening has side surfaces and extends through the dielectric layer, the first and second etch stop layers, and the first diffusion barrier layer, and the opening can also have rounded corners. A sidewall diffusion barrier layer can also be disposed on sidewalls of the via, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first metallization level includes a first metal feature, and metal within the opening forms a second metal feature.
By providing a first diffusion barrier layer to the material of the metallization level, the material of the first diffusion barrier layer can be subsequently sputtered onto the sidewalls of the opening. The material deposited on the sidewalls forms a new sidewall diffusion barrier layer that prevents contamination of the dielectric layer caused by the material of the metallization level being deposited on the sidewalls when this material is subsequently sputtered off. The sputtering process also advantageously provides the opening with round corners, which reduce the formation of voids in the opening.
In another aspect of the invention, the dielectric layer is formed from a low-k dielectric material, and this low-k dielectric material can have a dielectric constant of less than about 3.5. Furthermore, the low-k dielectric material can be formed with a porous material. Additionally, the semiconductor device can further comprise a capping layer disposed over the dielectric layer. By providing a dielectric layer formed from a low-k dielectric material, the capacitance of the dielectric layer is reduced as compared to dielectric layers formed using conventional dielectric materials.
In a further aspect of the invention, the material of the first diffusion barrier layer can include silicon nitride, and the thickness of the first diffusion barrier layer can be from about 80 angstroms to about 120 angstroms. The material of the second etch stop layer can include silicon oxide, and the material of the first etch stop layer can include silicon nitride. The thickness of the first etch stop layer can be from about 400 angstroms to about 600 angstroms. The metal and the first metallization level can comprise copper or a copper alloy. A second diffusion barrier layer can also be disposed over the sidewall diffusion barrier layer with a second interface therebetween.
In still another aspect of the invention, the opening can be a via opening, a trench or a dual damascene opening. The dual damascene opening can comprise a lower via opening in communication with an upper trench. Also, the second metal feature can be a via, a line, or a combination of a lower via in contact with an upper line.
In an additional embodiment of the present invention, a semiconductor device comprises a first metallization level; a dielectric layer disposed over the first metallization level; a first sidewall diffusion barrier layer formed on sidewalls of an opening; a second diffusion barrier layer disposed on the first sidewall diffusion barrier layer with an interface therebetween; and a conductive plug within the via. The opening extends through the dielectric layer to the first metallization level and can have rounded corners. The first sidewall barrier diffusion layer is formed by sputtering a first diffusion barrier layer disposed over the first metallization level.
In a further embodiment of the present invention, a method of manufacturing a semiconductor device is also disclosed. The method of manufacturing includes forming a first diffusion barrier layer over a first metallization level; forming a second etch stop layer over the first diffusion barrier layer; forming a first etch stop layer on the second etch stop layer with a first interface therebetween; depositing a dielectric layer over the first etch stop layer; etching the dielectric layer to form an opening through the dielectric layer and the first etch stop layer; and sputtering the first diffusion barrier layer and the second etch stop layer. The sputtering rounds corners of the opening and deposits material of the first diffusion barrier layer onto sidewalls of the opening to form a sidewall diffusion barrier layer.
In an additional aspect of the invention, the method can further include the steps of depositing a conductive material within the opening. Also, the dielectric layer can be formed from a low-k dielectric material, and the first metallization level and the conductive material can comprise copper or a copper alloy. The material of the first diffusion barrier layer and the first etch stop layer can include silicon nitride, and the material of the second etch stop layer can include silicon oxide.
In still another embodiment of the present invention, an additional method of manufacturing a semiconductor device is disclosed. The method of manufacturing includes forming a first metallization level; forming a first diffusion barrier layer over the first metallization level; forming a second etch stop layer over the first diffusion barrier layer; forming a first etch stop layer on the second etch stop layer with a first interface therebetween; forming a dielectric layer over the first etch stop layer; depositing a capping layer over the dielectric layer; depositing a resist over the capping layer; patterning the resist; etching the capping layer and the dielectric layer with a first etchant; etching the first etch stop layer with a second etchant; sputtering the first diffusion barrier layer and the second etch stop layer; depositing a conductive material in an opening and over a sidewall diffusion barrier layer; and planarizing a top surface of the capping layer. The etching of the capping layer, dielectric layer and the first etch stop layer forms the opening. The sputtering exposes the first metallization level, rounds corners of the opening, and also deposits material of the first diffusion barrier layer onto sidewalls of the opening to form the sidewall diffusion barrier layer.
In another aspect of the invention, the dielectric layer is formed from a low-k dielectric material, and this low-k dielectric material can have a dielectric constant of less than about 3.5. The material of the first diffusion barrier layer and the first etch stop layer can include silicon nitride, and the material of the first etch stop layer can include silicon oxide.
In still a further embodiment of the present invention, a semiconductor device comprises a first metallization level, a first diffusion barrier layer, a third etch stop layer, a second etch stop layer, a first dielectric layer, a first etch stop layer, a second dielectric layer, a trench, and a via opening. The first diffusion barrier layer is formed from a first material disposed over the first metallization level. The third etch stop layer is formed from a second material disposed over the first diffusion barrier layer, and the first material is different from the second material. The second etch stop layer is disposed on the third etch stop layer with a first interface therebetween, and the first dielectric layer is disposed over the second etch stop layer. The first etch stop layer is disposed over the first dielectric layer, and the second dielectric layer is disposed over the first etch stop layer. The trench extends through the second dielectric layer and the first etch stop layer, and the via opening extends from the trench through the first dielectric layer, the second and third etch stop layers, and the first diffusion barrier layer to the first metallization level. The via opening and the trench can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the via opening and trench, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first metallization level includes a first metal feature. A metal within the via the via and trench can respectively form a lower via and an upper trench.
By providing a first diffusion barrier layer to the material of the first metallization level, the material of the first diffusion barrier layer can be subsequently sputtered onto the sidewalls of the via opening and the trench. The material deposited on the sidewalls forms a new sidewall diffusion barrier layer that prevents contamination of the dielectric layers caused by the material of the first metallization level being deposited on the sidewalls when this material is subsequently sputtered off. The sputtering process also advantageously provides the via opening and trench with round corners, which reduce the formation of voids in the via opening and trench.
In another aspect of the invention, the dielectric layers are formed from a low-k dielectric material, and this low-k dielectric material can have a dielectric constant of less than about 3.5. Furthermore, the low-k dielectric material can be formed with a porous material. Additionally, the semiconductor device can further comprise a capping layer disposed over the second dielectric layer. By providing dielectric layers formed from a low-k dielectric material, the capacitance of the dielectric layers are reduced over dielectric layers formed with conventional dielectric materials.
In a further aspect of the invention, the material of the first diffusion barrier layer can include silicon nitride, and the thickness of the first diffusion barrier layer can be from about 80 angstroms to about 120 angstroms. The material of the third etch stop layer can include silicon oxide, and the material of the first and second etch stop layers can include silicon nitride. The thickness of the first and second etch stop layers can be from about 400 angstroms to about 600 angstroms. The metal and the first metallization level can comprise copper or a copper alloy. A second diffusion barrier layer can also be disposed over the sidewall diffusion barrier layer with a second interface therebetween.
In yet another embodiment of the present invention, a semiconductor device comprises a first metallization level; a first dielectric layer disposed over the first metallization level; a second dielectric layer disposed over the first dielectric layer; a first sidewall diffusion barrier layer disposed on sidewalls of a via opening and trench; a second diffusion barrier layer disposed on the first sidewall diffusion barrier layer with an interface therebetween; and conductive material within the via opening and trench. The trench extends through the second dielectric layer to the first dielectric layer, and the via opening extends from the trench through the first dielectric layer to the first metallization level. The via opening and trench can also have rounded corners. The first sidewall diffusion barrier layer is formed by sputtering a first diffusion barrier layer disposed over the first metallization level.
In a further embodiment of the present invention, a method of manufacturing a semiconductor device is also disclosed. The method of manufacturing includes forming a first diffusion barrier layer over a first metallization level; forming a third etch stop layer over the first diffusion barrier layer; forming a second etch stop layer on the third etch stop layer with a first interface therebetween; forming a first dielectric layer over the second etch stop layer; forming a second dielectric layer over the first dielectric layer; etching the first and second dielectric layers to form a via opening and a trench; and sputtering the first diffusion barrier layer and the first etch stop layer. The trench is formed through the second dielectric layer and to the first dielectric layer, and the via opening is formed from the trench through the first dielectric layer, the second and third etch stop layers, the first diffusion barrier layer to the first metallization level. Also, the sputtering rounds corners of the via and trench and also deposits material of the first diffusion barrier layer onto sidewalls of the via opening and trench to form a sidewall diffusion barrier layer.
In an additional aspect of the invention, the method can further include the steps depositing a first etch stop layer between the first dielectric layer and the second dielectric layer and etching the first etch stop layer during etching of the second etch stop layer. The material of the first diffusion barrier layer can include silicon nitride, the material of the third etch stop layer can include silicon oxide, and the material of the first and second etch stop layers can include silicon nitride. A second diffusion barrier layer can also be deposited over the sidewall diffusion barrier layer with a second interface therebetween, and a conductive material can then be deposited within the via opening and trench. The dielectric layers can also be formed from a low-k dielectric material.
In still another embodiment of the present invention, an additional method of manufacturing a semiconductor device is disclosed. The method of manufacturing includes forming a first metallization level; forming a first diffusion barrier layer over the first metallization level; forming a third etch stop layer over the first diffusion barrier layer; forming a second etch stop layer on the third etch stop layer with an interface therebetween; forming a first dielectric layer over the second etch stop layer; forming a first etch stop layer over the first dielectric layer; forming a second dielectric layer over the first etch stop layer; forming a capping layer over the second dielectric layer; forming a first resist over the capping layer; patterning the first resist; etching the capping layer and the second dielectric layer with a first etch; etching the first etch stop layer with a second etch; forming a second resist over the capping layer; patterning the second resist; etching the capping layer and first and second dielectric layers with a third etch; etching the first and second etch stop layers with a fourth etch; sputtering the first diffusion barrier layer and the third etch stop layer; depositing a conductive material in a via opening and a trench; and planarizing a top surface of the capping layer. The etchings form the trench through the capping layer, the second dielectric layer, and the first etch stop layer to the first dielectric layer and form the via opening from the trench through the first dielectric layer and the second etch stop layer to the third etch stop layer. The sputtering exposes the first metallization level, rounds corners of the via and trench, and deposits material of the first diffusion barrier layer onto sidewalls of the via opening and trench to form a sidewall diffusion barrier layer. The conductive layer is also deposited over the sidewall diffusion barrier layer. The material of the first and second etch stop layers and the first diffusion barrier layer can include silicon nitride, and the material of the third etch stop layer can include silicon oxide. Also, the dielectric layers can be formed from a low-k dielectric material.